ACTEL系列IC芯片解密是目前芯片解密行業(yè)的高難度IC解密系列，該系列芯片的加密性極高，解密難度極大，特別是ACTEL公司新推出的ProASIC3系列等典型FPGA芯片系列，大部分型號(hào)目前在國內(nèi)外均無破解先例。
　　針對ACTEL系列高難度IC芯片解密，龍人也專門組織了高級解密工程師進(jìn)行攻關(guān)研究，目前來說，技術(shù)攻關(guān)已經(jīng)取得階段性進(jìn)展，部分高難度芯片的解密方案已經(jīng)正式推出，而且針對多種高難度解密芯片，工程師也可以提供方案開發(fā)服務(wù)。
　　提醒廣大客戶，ACTEL系列芯片解密由于難度極大，解密費(fèi)用相對較高，解密周期較長，如果客戶確實(shí)有解密需求，可以先提供相關(guān)期間給我們進(jìn)行分析與測試，而且需要做好相關(guān)的預(yù)算，并考慮到風(fēng)險(xiǎn)性的存在。

Features and Benefits

• 1.2 V to 1.5 V Core Voltage Support for Low Power

• Supports Single-Voltage System Operation

• 5 μW Power Consumption in Flash*Freeze Mode

• Low-Power Active FPGA Operation

• Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze Mode

• 15 k to 1 Million System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

• 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design When Powered Off

• 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

Performance

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption (except ARM®-enabled IGLOO®

devices) via JTAG (IEEE 1532–compliant)†

• FlashLock® to Secure FPGA Contents

• Segmented, Hierarchical Routing and Clock Structure

• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X†, and

LVCMOS 2.5 V / 5.0 V Input†

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and MLVDS

(AGL250 and above)

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os‡

• Programmable Output Slew Rate† and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

• Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay

Capabilities, and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit† RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

• True Dual-Port SRAM (except ×18)†

• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available

with or without Debug

 

AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 AGLE600 

AGLE3000 AGLN010 AGLN015 AGLN020 AGLN0301 AGLN060 AGLN125

AGLN250 AGLP030 AGLP060 AGLP125